Designed and implemented a custom CPU in Verilog HDL, applying core computer architecture principles including instruction execution, datapath design, and control logic.

Built and simulated a hardware-level processor architecture to explore how instructions are fetched, decoded, and executed at the RTL level.

• Developed a modular CPU architecture in Verilog including ALU, control unit, registers, and datapath components.
• Implemented instruction decoding and execution logic following a simplified ISA design.
• Simulated hardware behavior using standard RTL verification workflows.
• Explored fundamental computer architecture concepts including pipelining (if applicable), control flow, and signal timing.
• Validated CPU functionality through testbenches and simulation-driven verification.